`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    21:06:33 05/01/2014 
// Design Name: 
// Module Name:    boss 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module boss(enable, Xpheonix, Ypheonix,blank,hcount,vcount,clk,rst,pheonix,pheonix_sprite);

	input clk,rst,enable,blank;
	input [10:0] hcount,vcount;
	input [9:0] Xpheonix, Ypheonix;
	output [7:0] pheonix_sprite;
	output	pheonix;

	parameter 	DELAY = 25;
	parameter PHEONIX_SIZE = 9216;
	
	wire [7:0] pixel_color;

	reg [5:0]	frame_delay;
	reg [15:0] 	pheonix_count;
	reg [1:0]	frame;

	le_boss pheonixes(
		.clka(clk), 					// input clka
		.wea(1'b0), 					// input [0 : 0] wea
		.addra(pheonix_count), 				// input [15 : 0] addra	*****
		.dina(8'd0), 						// input [7 : 0] dina
		.douta(pheonix_sprite) 		// output [7 : 0] dout
	);
	
	initial begin
			frame <= 0;
			frame_delay <=0;
	end

	always @ (posedge clk) begin

		if (rst) begin
			frame <= 0;
			frame_delay <=0;
			pheonix_count <= 0;
		end
		
		else if (pheonix) begin
						
			pheonix_count <= pheonix_count + 1'b1;
			
   		case (frame)
			0: begin
					if (pheonix_count == (PHEONIX_SIZE*1)-1) begin 
						if (frame_delay >= DELAY) begin
							frame_delay <= 0;
							frame <= 1;
						end
						else begin
							pheonix_count <= 0;
							frame_delay <= frame_delay + 1'b1;
						end
					end
				end
			1: begin
					if (pheonix_count == (PHEONIX_SIZE*2)-1) begin
						if (frame_delay >= DELAY) begin
							frame_delay <= 0;
							frame <= 2;
						end
						else begin
							pheonix_count <= PHEONIX_SIZE;
							frame_delay <= frame_delay + 1'b1;
						end
					end
				end
			2: begin
					if (pheonix_count == (PHEONIX_SIZE*3)-1) begin
						if (frame_delay >= DELAY) begin
							frame_delay <= 0;
							frame <= 3;
							pheonix_count <= PHEONIX_SIZE;
						end
						else begin
							pheonix_count <= PHEONIX_SIZE*2;
							frame_delay <= frame_delay + 1'b1;
						end
					end
				end
			3: begin
					if (pheonix_count == (PHEONIX_SIZE*2)-1) begin
						if (frame_delay >= DELAY) begin
							frame_delay <= 0;
							frame <= 0;
							pheonix_count <= 0;
						end
						else begin
							pheonix_count <= PHEONIX_SIZE;
							frame_delay <= frame_delay + 1'b1;
						end
					end
				end
			default: begin
					if (pheonix_count == (PHEONIX_SIZE*1)-1) begin 
						if (frame_delay >= DELAY) begin
							frame_delay <= 0;
							frame <= 1;
						end
						else begin
							pheonix_count <= 0;
							frame_delay <= frame_delay + 1'b1;
						end
					end
				end
			endcase
		
		end
	end
		
	assign pheonix1 = ~blank & (hcount >= Xpheonix & hcount <= Xpheonix+95 & vcount >= Ypheonix & vcount <= Ypheonix+95);
	assign pheonix2 = ~blank & (hcount >= 700 & hcount <= 700 & vcount >= 600 & vcount <= 600);
	
	assign pheonix = enable? pheonix1 : pheonix2;
endmodule
